Memory device with programmable receivers to improve performance
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United States of America Patent
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Jan 12, 2010
Grant Date -
May 19, 2005
app pub date -
Nov 18, 2003
filing date -
Nov 18, 2003
priority date (Note) -
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Abstract
A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.
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