Applications of cascading DSP slices
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United States of America Patent
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Jul 28, 2009
Grant Date -
Jun 30, 2005
app pub date -
Dec 21, 2004
filing date -
Dec 29, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
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