Electrochemical etching of circuitry for high density interconnect electronic modules
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United States of America Patent
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Issued Date -
Jul 7, 2005
app pub date -
Dec 29, 2003
filing date -
Dec 29, 2003
priority date (Note) -
Abandoned
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Abstract
A method for electrochemically etching a metal layer deposited on a dielectric with an etch resist layer pattern to form circuitry for high density interconnect electronic modules using a nonactive electrolyte solution is described. The method is particularly useful for printed wiring boards, chip scale packages, wafer level packages and the like. The circuit tracks generally range from 50 to 125 micrometers for printed wiring boards, from 5 to 50 micrometers for chip scale packages, and from 0.1 to 5 micrometers for wafer level packages. In one embodiment of the invention the metal layer is copper and the nonactive electrolyte solution is a mixture of sodium nitrate and sodium chloride and a pulse electric current is employed to accomplish the electrochemical etching.
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