Importance

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Abstract

An interface source system providing at least two paths to load an instruction decode register of a coprocessor is disclosed. The interface source system includes an instruction port register, an instruction memory, an instruction decode register, and an interrupt vector table (IVT) stored in the instruction memory. The IVT stores an external instruction vector containing either a predetermined value indicating that the instruction decode register is to be loaded with contents from the instruction port register or an address of an instruction in the instruction memory. A first one of the at least two paths is used to load the instruction from the instruction memory containing the IVT if the external instruction vector contained the address of the instruction in the instruction memory. A second one of the at least two paths is used to load the instruction from the instruction port register if the external instruction vector contained the predetermined value.

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First Claim