Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays
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United States of America Patent
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May 9, 2006
Grant Date -
Jul 14, 2005
app pub date -
Aug 31, 2004
filing date -
Jan 14, 2004
priority date (Note) -
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Abstract
A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access transistors electrically coupled to a pair of FIFO read bit lines and a third pair of access transistors electrically coupled to a pair of memory read bit lines. A direct path data transfer circuit is provided. This transfer circuit is configured to support a unidirectional data transfer path that extends from first storage nodes within the first SRAM element to second storage nodes within the second dual-port SRAM element. This transfer circuit is also responsive to a direct path word line signal.
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