Importance

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Abstract

A method of operation of a memory device and a memory device having registers to store values representing a number of clock cycles to access and output data is provided in embodiments. Data is sensed from an array of memory cells using a plurality of sense amplifiers. A column address that identifies data sensed is latched using the plurality of sense amplifiers. The data is accessed, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address. The first number of clock cycles is represented by a first value stored in a first register on the memory device. The data is output after a second number of clock cycles have elapsed after accessing the data from the array of memory cells. The second number of clock cycles is represented by a second value stored in a second register on the memory device. A column decoder driving a column select line based on the column address accesses the data.

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First Claim