Direct memory access controller system with message-based programming
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United States of America Patent
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Jan 31, 2012
Grant Date -
Jul 28, 2005
app pub date -
Mar 23, 2005
filing date -
Dec 19, 2002
priority date (Note) -
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Abstract
A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.
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