Micro pin grid array with pin motion isolation
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United States of America Patent
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May 4, 2010
Issued Date -
N/A
app pub date -
Nov 10, 2004
filing date -
Dec 30, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.
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