Atomic layer deposition of CMOS gates with variable work functions
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United States of America Patent
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app pub date -
Jan 20, 2005
filing date -
Aug 22, 2002
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Abstract
According to one aspect, a CMOS device includes a PMOS transistor and an NMOS transistor, where each transistor includes a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator. The gate of the PMOS transistor includes a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function. The gate of the NMOS transistor includes a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude. At least one of the gates includes a ternary metal conductor formed by atomic layer deposition.
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