Method of forming wiring structure and semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7358180
APP PUB NO 20050194691A1
SERIAL NO

10927006

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • FUJITSU SEMICONDUCTOR LIMITED

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sakai, Hisaya Kawasaki, JP 22 185
Shimizu, Noriyoshi Kawasaki, JP 137 1425

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation