Parallel multithread processor (PMT) with split contexts
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United States of America Patent
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Apr 28, 2009
Grant Date -
Sep 8, 2005
app pub date -
Nov 12, 2004
filing date -
Nov 14, 2003
priority date (Note) -
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Abstract
The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).
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