Importance

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Abstract

Each non-volatile memory cell of an array of includes a guiding gate extending along a first portion of the cell's channel and a control gate extending along a second portion of the cell's channel. The first and second portions of the channel do not overlap. The guiding gate, which overlays the substrate above the channel, is insulated from the substrate via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. Each row of the array has a first terminal coupled to the guiding gates, and a second terminal coupled to the control gates of the cells disposed in that row. Each column of the array has a first terminal coupled to the drain regions, and a second terminal coupled to the source regions of the cells disposed in that column.

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First Claim