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Abstract

A data processing apparatus adopting a pipeline processing system, includes an instruction memory which store instruction packets; and a processing unit configured to execute the instruction packets sequentially in a pipeline manner. The processing unit includes an instruction queue and a loop speed-up circuit. The instruction packets stored in the instruction queue are executed sequentially by the processing unit. The loop speed-up circuit stores the instruction packets read out from the instruction memory into the instruction queue sequentially, holds the instruction packet containing a loop start address for a loop process, and outputs the held instruction packet to the instruction queue, when a loop process end is detected and the loop process is not circulated for a predetermined number of times.

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First Claim