Die with discrete spacers and die spacing method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20050224959A1
SERIAL NO

10966574

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A semiconductor die, for use in a multiple-die semiconductor chip package, has a wire bonding side and a backside. At least two discrete spacers, and preferably at least four, are secured to the die at chosen spacer positions on at least one of the wire bonding side and the backside. The spacers are configured and positioned to help maintain proper die-to-die spacing between the die and an adjacent die in a multiple-die semiconductor chip package. At least two of the discrete spacers may be secured directly to the wire bonding side. A dielectric layer may be on the backside of the die and at least two of the discrete spacers may be secured to the dielectric layer on the backside of the die.

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Patent Owner(s)

Patent OwnerAddress
CHIPPAC INC47400 KATO ROAD FREMONT CA 94538

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Geun Sik Sungnam, KR 8 214
Kwon, Hyeog Chan Seoul, KR 27 384

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