Shift and recode multiplier
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United States of America Patent
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Issued Date -
Oct 13, 2005
app pub date -
Apr 12, 2004
filing date -
Apr 12, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method and apparatus are provided for multiplying a multiplicand by a multiplier. The method and apparatus generate a plurality of partial products. Each partial product has a plurality of bits having respective binary weights, wherein each bit can have a first or second logic state. A first set of multiple-bit columns is formed from bits of the plurality of partial products, wherein the bits in each column of the first set have the same binary weight. Each multiple-bit column in the first set is encoded into a respective modified partial product, which represents a number of bits in the column having the first logic state. This process can be repeated until the number of partial products is reduces to a desired number.
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