Optimized system-level simulation
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United States of America Patent
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N/A
Issued Date -
Oct 13, 2005
app pub date -
Apr 8, 2004
filing date -
Apr 8, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Integration of a system-level simulation with one or more hardware device simulations is accomplished using a mapping layer, which allows the system-level simulation to interact with the hardware device simulation at a pin level, an object level, and an abstract level. The overall simulation may operate with respect to a clock or timing device or it may operate with respect to transactions.
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