Importance

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Abstract

PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, VCDLs provide for faster signal locking than do VCOs. The VCO locks to a frequency of a reference signal at substantially the same time that the VCDL locks to the reference signal. Lock time of the PLL circuit is thereby reduced. A timing circuit prevents the VCO control voltage from being adjusted during phase locking of the VCO. This allows the VCO frequency lock to be maintained during the VCO phase locking. Lock time is thereby further reduced. The timing circuit locks the VCO to a phase of the reference signal by restarting oscillation of the VCO at an appropriate time.

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First Claim