Packet counters and packet adders for traffic profiling in a multiprocessor router
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United States of America Patent
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Dec 1, 2009
Grant Date -
Nov 10, 2005
app pub date -
Dec 21, 2004
filing date -
May 7, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A packet counter/adder for use in a multiprocessor system. The packet counter stores a counter value of data packets processed by a plurality of processors in the multiprocessor system. The packet counter comprises a first register capable of storing the counter value, wherein the counter value in the first register is incremented by a write operation to a first address associated with the first register. The counter value in the first register may be set to a specified value by a write operation to a second address associated with the first register.
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