Address generators integrated with parallel FFT for mapping arrays in bit reversed order
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United States of America Patent
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app pub date -
Jul 22, 2005
filing date -
Mar 15, 2002
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Abandoned
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Abstract
Reducing the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Enables the design of address generators that combine IPBR and one FFT stage in parallel. Increases efficiency by removing instructions to store output from a stand-alone IPBR mapping and then fetch the same data as input for the FFT stage.
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