Dual damascene trench formation to avoid low-K dielectric damage

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United States of America Patent

PATENT NO 7169701
APP PUB NO 20060003576A1
SERIAL NO

10882058

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Abstract

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A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chao-Cheng Shin-chu County, TW 224 2653
Wu, Tsiao-Chen Hsinchu County, TW 25 376
Yeh, Chen-Nan Taipei, TW 46 2539

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