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Abstract

A register file in which the physical row/column mapping is decoupled from the logical row/column mapping. The physical register file includes R*C N-bit storage elements arranged in R rows and C columns. Each physical row includes an N-bit bus, a log.sub.2(C)-bit storage element selection line, and a log.sub.2(C)-bit output column selection line. In either a logical row or logical column access, no more than one storage element is selected per physical row and coupled to that row's bus, and each column's vertical bit line is uniquely coupled to one row's bus. The values on the storage element selection lines and on the output column selection lines determines which storage elements are coupled to which vertical bit lines. The width C of the register file, the number of rows R of the register file, and the size N of the fundamental data storage element can be independently changed without affecting the others. The size X of the X*N-bit logical data elements can be changed without changing R, C, N, or the width of the buses. The same addressing logic is used, regardless of data size and regardless of whether the access is logically row-wise or column-wise. Horizontal wire count is minimized by an appropriate logical-to-physical mapping of the storage cells.

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