High level validation of designs and products

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7275231
APP PUB NO 20060059444A1
SERIAL NO

10941324

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a relationship of messages communicated between multiple processes; resolving at least one scenario from the message diagram, wherein the scenario comprises a particular sequence of messages identified by the message diagram; generating a state machine operable to receive and transmit at least some of the messages identified by the message diagram according to the scenario; and testing an implementation of the design using the state machine.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Murthy, Praveen Kumar Fremont, CA 5 44
Rajan, Sreeranga P Sunnyvale, CA 47 2242
Takayama, Koichiro Tokyo, JP 21 326

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