Polysilicon sidewall spacer lateral bipolar transistor on SOI
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United States of America Patent
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Issued Date -
Mar 23, 2006
app pub date -
Aug 25, 2005
filing date -
Aug 27, 2004
priority date (Note) -
Abandoned
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Abstract
Consistent with an aspect of the present invention, a lateral bipolar transistor is provided that exhibits similar performance as that of high speed vertical bipolar junction transistors. The lateral bipolar transistor includes a polysilicon side-wall-spacer (PSWS) that forms a contact with the base of the transistor, and thus avoids the process step of aligning a contact mask to a relatively thin base region. The side wall spacer allows self-alignment of the base/emitter region, and has reduced base resistance and junction capacitance. Accordingly, improved cutoff frequency (f.tau.) and maximum oscillation frequency (fmax) can be achieved. Moreover, this novel topology enables the realization of Bipolar CMOS (BiCMOS) technology on insulating substrates, such as SOI.
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