Reordering packets
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United States of America Patent
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Dec 21, 2010
Issued Date -
N/A
app pub date -
Sep 27, 2005
filing date -
Jan 11, 2002
priority date (Note) -
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Abstract
There are disclosed processes and apparatus reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.
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