Electronic memory with binary storage elements
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United States of America Patent
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Apr 1, 2008
Grant Date -
Apr 20, 2006
app pub date -
Dec 2, 2005
filing date -
Feb 5, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.
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