Circuit board with reduced simultaneous switching noise
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United States of America Patent
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-
N/A
Issued Date -
May 25, 2006
app pub date -
Jul 19, 2005
filing date -
Nov 19, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A circuit board with reduced simultaneous switching noise. The circuit board comprises a first conductor plane with a first fixed potential, a dielectric layer, at least a build-up via and a second conductor plane with a second fixed potential. The dielectric layer is formed on the first conductor plane. The build-up vias are formed in the dielectric layer and filled with a conductive material. The second conductor plane is in contact with the conductive material in the build-up vias. The depth of the build-up vias is less than one fourth of a signal wavelength.
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