Floor plan for scalable multiple level tab oriented interconnect architecture
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United States of America Patent
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Oct 24, 2006
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N/A
app pub date -
Jan 4, 2006
filing date -
May 3, 1995
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Expired
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Abstract
A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network comprises a first plurality of switches coupling the first level routing resources to an intermediate tab and the intermediate tab coupling the second level routing resources through a second plurality of switches, each switch may comprise an additional buffer. Repeated applications of tab networks provide connections between lower level routing resources to higher level routing resources.
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