Importance

Loading Importance Indicators...

Abstract

The present invention relates to a method and apparatus for accelerating the display of horizontal lines used in an embedded system. The embedded system comprising a CPU (Central Processing Unit), a display terminal, a video memory for storing one or more display data, each data corresponds to a respective pixel on the display terminal, and a display-driving circuit for generating logic signals to read the display data from the video memory and delivering the display data to the display terminal for display, the apparatus for accelerating the display of horizontal lines comprising: a video memory controller, coupled to the CPU, the display-driving circuit and the video memory, for receiving from the CPU all request signals for performing reading and writing operations with the video memory, generating respective logic signals in response to the request signals and controlling the operations of reading data from or writing data into the video memory; a FIFO (First-In First-Out) buffer, coupled to a CPU bus, for, when the CPU provides an instruction for performing an operation of writing data into the video memory, buffering a control word sent by the CPU to the video memory controller, and the starting address for writing data into the video memory and the data to be written; and a line-accelerating register, comprising a length register for registering a line length value from the CPU and a line-accelerating flag for indicating an instruction for displaying a point or displaying a line from the CPU, wherein the FIFO buffer is also coupled to the output of the line-accelerating register and the FIFO buffer outputs a signal indicating whether it's empty or not to the video memory controller.

Loading the Abstract Image...

First Claim