PACKAGED CHIP CAPABLE OF LOWERING CHARACTERISTIC IMPEDANCE
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United States of America Patent
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N/A
Issued Date -
Jun 22, 2006
app pub date -
Feb 15, 2005
filing date -
Dec 16, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A packaged chip lowering characteristic impedance comprises a chip, a lead wire frame, a plurality of metal layers, adhesive layers, lead wires, and a mold, being formed into TSOP LOC and thin-small-sized packaging types; from a specified site above or under each row of leads of the lead wire frame, metal layers are fixed respectively with adhesives layers to the lead wire frame; lead wires are connected respectively between electrode contacts of the chip and leads of the lead wire frame and a lead wire provided is connected between at least one lead and the metal layer, so the packaged chip using metal layers as a Ground or Power plane is formed; thus, electrical noises and EMI are lowered and a problem of poor transmission of signals is eliminated so that a stable transmission of signals and an efficient transmission speed may be further developed.
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