Multi-thickness dielectric for semiconductor memory
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United States of America Patent
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Jan 27, 2009
Grant Date -
Jun 22, 2006
app pub date -
Dec 22, 2004
filing date -
Dec 22, 2004
priority date (Note) -
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Abstract
A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.
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