Charge trap insulator memory device
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United States of America Patent
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Issued Date -
Jun 29, 2006
app pub date -
Apr 27, 2005
filing date -
Dec 29, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A charge trap insulator memory device comprises a bottom word line, a P-type float channel formed at the bottom word line and kept at a floating state, a charge trap insulator formed on the P-type float channel, a top word line formed on the charge trap insulator in parallel with the bottom word line, and a N-type drain region and a N-type source region formed at both sides of the float channel. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.
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