Hierarchical packet scheduler using hole-filling and multiple packet buffering

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United States of America Patent

PATENT NO 7646779
APP PUB NO 20060140201A1
SERIAL NO

11020942

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Abstract

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A hierarchical packet scheduler using hole-filling and multiple packet buffering. Packet references are enqueued into a hierarchical packet scheduler, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers being served by one or more threads, wherein the number of threads serving a particular level is not dependent on the number of schedulers on the particular level. Packet references are dequeued from the hierarchical packet scheduler at a root level scheduler of the one or more schedulers.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kounavis, Michael Hillsboro, US 37 318
Kumar, Alok Santa Clara, US 110 2427
Yavatkar, Raj Portland, US 63 2154

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