Diode structure for word-line protection in a memory circuit
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United States of America Patent
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Issued Date -
Jul 6, 2006
app pub date -
Jan 5, 2005
filing date -
Jan 5, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.
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