Reducing memory access bandwidth consumption in a hierarchical packet scheduler

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7525962
APP PUB NO 20060153184A1
SERIAL NO

11024318

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Reducing memory access bandwidth consumption in a hierarchical packet scheduler. A hierarchical packet scheduler is maintained, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers, wherein one or more threads serve each level. Scheduling operations are performed at each scheduler of the hierarchical packet scheduler by reading a portion of scheduler state from external memory.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA29226

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kounavis, Michael Hillsboro, US 17 116
Kumar, Alok Santa Clara, US 77 1300
Yavatkar, Raj Portland, US 31 813

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Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTEL CORPORATION (3)
9461930 Modifying data streams without reordering in a multi-thread, multi-flow network processor 0 2012
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AGFA HEALTHCARE NV (1)
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* Cited By Examiner

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