Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory
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United States of America Patent
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Jun 2, 2009
Grant Date -
Jul 20, 2006
app pub date -
Jan 5, 2006
filing date -
Jan 20, 2005
priority date (Note) -
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Abstract
A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU. The CPU fetches and executes program instructions from a CPU memory coupled to it. The CPU programs the bus bridge with window information defining a window of locations within the CPU memory, which is less than an entirety of the CPU memory. The bus bridge receives data on the link from the other controller and if the header of a packet containing the data indicates it is destined for the CPU memory, the bus bridge translates the address of the data so as to write the data safely to the CPU memory, but only within the window and nowhere else within the CPU memory.
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