Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics

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United States of America Patent

PATENT NO 7323386
SERIAL NO

11375975

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Abstract

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A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the 'drift' region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 .ANG. gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

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Patent Owner(s)

Patent OwnerAddress
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED475 OAKMEAD PKWY SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Yilmaz, Hamza Saratoga, CA 249 3656

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