Vertical stacking of multiple integrated circuits including SOI-based optical components
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United States of America Patent
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Issued Date -
Aug 10, 2006
app pub date -
Feb 3, 2006
filing date -
Feb 4, 2005
priority date (Note) -
Abandoned
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Abstract
A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input/output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input/output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| CISCO TECHNOLOGY INC | 170 WEST TASMAN DRIVE SAN JOSE CA 95134 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Fangman, John | Leesport, PA | 11 | 169 |
| Patel, Vipulkumar | Breinigsville, PA | 109 | 2141 |
| Piede, David | Allentown, PA | 30 | 779 |
| Shastri, Kalpendu | Orefield, PA | 76 | 1652 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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