Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
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United States of America Patent
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Feb 2, 2010
Grant Date -
Aug 10, 2006
app pub date -
Feb 4, 2005
filing date -
Feb 4, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.
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