Trimming fuse circuit with latch

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20060181331A1
SERIAL NO

11346347

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Abstract

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A trimming fuse circuit with a latch is disclosed. The trimming fuse circuit includes: a first CMOS transistor having a first PMOS and a second NMOS, wherein said first PMOS has a size smaller than that of said first NMOS; a second CMOS transistor having a second PMOS and a second NMOS, wherein said second PMOS has a size larger than that of said second NMOS, and still an input terminal of said second CMOS is cross-coupled with an output terminal of said first CMOS, furthermore, an output terminal of said first CMOS is cross-coupled with an input terminal of said second CMOS; and a fuse connected in between said input terminal of said first CMOS transistor and ground; thus, outputting an voltage high control signal from said output terminal of said first CMOS while said voltage high fuse is not burned-out; and outputting an voltage low control signal voltage low whiles said fuse is burned-out.

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Patent Owner(s)

Patent OwnerAddress
NEOTEC SEMICONDUCTOR LTD4F NO 32 TAI-YUEN STREET CHU-PEI HSIN-CHU HSIEN 302

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Uladzimir, Fomin Minsk, BY 3 4

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