Systems for performing parallel distributed processing for physical layout generation
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United States of America Patent
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Issued Date -
Sep 7, 2006
app pub date -
Dec 22, 2005
filing date -
Mar 4, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system for performing parallel distributed processing thereby accelerating the generation of a physical layout is disclosed. Specifically, the system significantly reduces the execution time of a place and route stage in the design of an integrated circuit (IC). An IC design is broken to multiple tiles that are independently processed and routed in parallel. This is achieved by providing an infrastructure that manages the multi-processing as well as data flows between a main computing node and a plurality of remote processing nodes.
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