Low capacitance solder bump interface structure
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United States of America Patent
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N/A
Issued Date -
Sep 14, 2006
app pub date -
Mar 8, 2006
filing date -
Mar 8, 2005
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A method for controlling capacitance associated with solder sphere bumps is provided. An improved structure is proposed which uses a much smaller pad on an IC with standard chip dielectric and passivation layers. An additional thick dielectric layer is then applied to the structure and a small via is opened in this thick dielectric layer. An under bump metal (UBM) is deposited and defined to provide a chip to solder sphere bump interface and an electrical connection between the pad and the solder sphere bump. The solder sphere bump can then be attached and reflowed to the UBM. Practical implementations of the invention typically obtain factors of reduction in capacitance of at least 10-20.
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