Printed circuit patterned embedded capacitance layer
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United States of America Patent
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Nov 21, 2006
Grant Date -
Sep 21, 2006
app pub date -
Mar 21, 2005
filing date -
Mar 21, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.
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