Clock synchronization in a multistage switch structure
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 21, 2006
app pub date -
Dec 14, 2005
filing date -
Dec 15, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A clock synchronizing method in a multistage switch structure comprises providing a first reference clock signal to a first switch via a first clock recovery unit; providing a second reference clock signal to a second switch via a Phase Lock Loop (PLL); and providing a third reference clock signal to a third switch via a second clock recovery unit to synchronize first, second and third switches.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully