Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
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United States of America Patent
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May 13, 2008
Issued Date -
N/A
app pub date -
Mar 31, 2006
filing date -
Mar 31, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other, that is, the die attach sides of the package substrates face one another, and the 'land' sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. One or more additional components may be stacked over the land side of the first package substrate.
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