Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
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United States of America Patent
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Sep 30, 2008
Grant Date -
Oct 5, 2006
app pub date -
Mar 31, 2006
filing date -
Mar 31, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second ('land') side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated with both the land side of the second substrate and a portion of the land side of the first package substrate exposed, so that second level interconnection and interconnection with additional components may be made.
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