Circuit and method for transistor turn-off with strong pulldown
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United States of America Patent
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Jun 29, 2010
Grant Date -
Oct 5, 2006
app pub date -
Mar 30, 2005
filing date -
Mar 30, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to avoid inadvertent or false turn ons. A strong pulldown is provided to the gate of a power FET to avoid inadvertent turn on during output swings. In other cases, the gate of the power FET is pulled down weakly to reduce EMI and voltage noise in the circuit. In a particular exemplary embodiment, the present invention provides a circuit and method for obtaining a strong pulldown on the gate of a power FET in an off state, while providing a weak pulldown during turn on to turn off transitions. The invention avoids false turn ons during fast output transitions while maintaining relatively high EMI protection.
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