Decoding circuit for non-binary groups of memory line drivers
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United States of America Patent
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-
Sep 18, 2007
Grant Date -
Oct 5, 2006
app pub date -
Jun 7, 2005
filing date -
Mar 31, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
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