Importance

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Abstract

Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells by different amounts.

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First Claim