Method and apparatus for incorporating block redundancy in a memory array
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United States of America Patent
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Nov 28, 2006
Issued Date -
N/A
app pub date -
Mar 31, 2005
filing date -
Mar 31, 2005
priority date (Note) -
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Abstract
An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
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