Digital signal processing circuit having input register blocks
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United States of America Patent
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Nov 23, 2010
Issued Date -
N/A
app pub date -
May 12, 2006
filing date -
Dec 29, 2003
priority date (Note) -
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Abstract
An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.
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